(Presentation - presented in hybrid/virtual, Oct. 2020) Keynote talk at the High-performance Interconnects Forum (in conjunction with HPC China 2020)
Abstract
Remote memory access (RDMA) networks have been around for more than a decade. RDMA hardware enables basic put/get operations into userlant at very high speeds and reduces CPU overheads significantly. However, we observe that CPU requirements for processing data at modern speeds of 400 or 800 Gbit/s are still huge. Modern smart NICs add various processing capabilities ranging from fully-fledged ARM cores to FPGA-accelerated NICs. However, all current implementations are either relatively inefficient for line-rate packet processing or offer only limited functions such as header rewriting. We advocate for a fully flexible model that allows to execute arbitrary C code on each packet. We show that 'streaming Processing in the Network' (sPIN) enables such a model. Our implementation based on RISC-V demonstrates that generic network acceleration is feasible and delivers an efficiency improvement of up to 100x. We release our implementations as open source and expect that more vendors will adopt generic in-network computations in addition to RDMA.
Documents
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Recorded talk (best effort)
BibTeX
@misc{hoefler-hpcchina20, author={Torsten Hoefler}, title={{General in-network processing - time is ripe!}}, year={2020}, month={Oct.}, location={hybrid/virtual}, source={http://www.unixer.de/~htor/publications/}, }
